1. Field of the Invention
The present invention relates to computer processing apparatus and methods in which an enhanced Harvard Architecture is used in applications such as portable hand-held computing devices, where operating system code, application code, and read-only data are contained in ROM and user data and some application code are in RAM.
2. Description of the Related Art
Currently available microprocessors typically use one of two known architectures for interfacing to memory. These architectures are known as Von Neumann architecture and Harvard Architecture. The memory interfaced to the microprocessor may be integrated with the microprocessor on the same chip or be located external to the microprocessor chip.
In Von Neumann architecture, as shown in FIG. 1, a microprocessor is linked by one interface to a single memory system which is used to store both program instructions and data. Therefore, only program instruction code or data can be transferred to the microprocessor at any given time but not both simultaneously. Conventional Harvard architecture, as shown in FIG. 2, was devised to speed up operation of computers by allowing simultaneous access of program instructions and data which are stored in separate memories. A separate bus interface is provided for each of the two memories to make the simultaneous action possible.
As a result of this dual bus interface, a microprocessor utilizing conventional Harvard architecture requires less cycles to perform the same operations performed by a microprocessor utilizing Von Neumann architecture. This is so because, for example, in a microprocessor with conventional Harvard architecture, an instruction fetch from the program memory can be accomplished simultaneously with a data read/write request to or from data memory.
Thus, conventional Harvard architecture clearly has a performance advantage over Von Neumann architecture. Specifically, under conventional Harvard architecture, the bandwidth, which represents the amount of information (either data or code) transmitted in one cycle between devices, is increased with two interfaces operating simultaneously over separate buses. For this reason, conventional Harvard architecture is commonly found in high performance systems.
There are, however, drawbacks with conventional Harvard architecture which relate to the lack of flexibility in how the memory systems connected to the two interfaces may be used. Problems resulting from this lack of flexibility include: the need to separate program code and read-only data, the inability to support self-modifying code (which requires that the microprocessor be able to modify program memory using data accesses) and increased complexity when testing program memory.
The microprocessor may use non-volatile solid state memory or a mass storage medium such as a hard disk for storing operating system and user application code. Many of these embedded applications require low cost, minimum power dissipation, and low weight. Accordingly, a typical embedded application would use a non-volatile memory such as ROM. The ROM typically contains the operating system code, user application code, and read-only data. ROM access time is generally slower than RAM access time. In systems that use ROM, this deficiency leads to system performance degradation.
Therefore, it is desirable to use a more efficient microprocessor architecture, such as Harvard architecture, which is faster than the Von Neumann architecture in order to make up for the performance degradation associated with ROM. However, since ROM may contain both program instructions, including self-modifying code, and read-only-data, a conventional Harvard architecture approach having dedicated program instruction and data memories each on their own bus would not work in this particular application.
The inability to access program memory as data makes the task of testing program memory more difficult. There are well established procedures which currently exist for testing both RAM and ROM when the microprocessor is able to access the memories through data accesses. These known procedures are different for ROM and RAM. ROM is typically tested through the use of cyclic redundancy checking ("CRC") or checksums which require reading every entry in the ROM. RAM may be tested by writing and then reading known patterns of data and address sequences or built-in-self-test.
Accordingly, a need exists for a computer system architecture for use in mobile or portable computing and high performance system applications, which provides the advantages of the dual bus interface of conventional Harvard architecture while supporting read-only data and self-modifying code wherein both instructions and data may be stored in each of two memory storage areas connected to the microprocessor by independent buses.